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general description the MAX109, 2.2gsps, 8-bit, analog-to-digital converter (adc) enables the accurate digitizing of analog signals with frequencies up to 2.5ghz. fabricated on an advanced sige process, the MAX109 integrates a high- performance track/hold (t/h) amplifier, a quantizer, and a 1:4 demultiplexer on a single monolithic die. the MAX109 also features adjustable offset, full-scale volt- age (via refin), and sampling instance allowing multi- ple adcs to be interleaved in time. the innovative design of the internal t/h amplifier, which has a wide 2.8ghz full-power bandwidth, enables a flat-frequency response through the second nyquist region. this results in excellent enob perfor- mance of 6.9 bits. a fully differential comparator design and decoding circuitry reduce out-of-sequence code errors (thermometer bubbles or sparkle codes) and provide excellent metastability performance (10 14 clock cycles). this design guarantees no missing codes. the analog input is designed for both differential and single-ended use with a 500mv p-p input-voltage range. the output data is in standard lvds format, and is demultiplexed by an internal 1:4 demultiplexer. the lvds outputs operate from a supply-voltage range of 3v to 3.6v for compatibility with single 3v-reference systems. control inputs are provided for interleaving additional MAX109 devices to increase the effective system-sampling rate. the MAX109 is offered in a 256-pin super ball-grid array (sbga) package and is specified over the extended industrial temperature range (-40? to +85?). applications radar warning receivers (rwr) light detection and ranging (lidar) digital rf/if signal processing electronic warfare (ew) systems high-speed data-acquisition systems digital oscilloscopes high-energy physics instrumentation ate systems features ? ultra-high-speed, 8-bit, 2.2gsps adc ? 2.8ghz full-power analog input bandwidth ? excellent signal-to-noise performance 44.6db snr at f in = 300mhz 44db snr at f in = 1600mhz ? superior dynamic range at high-if 61.7dbc sfdr at f in = 300mhz 50.3dbc sfdr at f in = 1600mhz -60dbc im3 at f in1 = 1590mhz and f in2 = 1610mhz ? 500mv p-p differential analog inputs ? 6.8w typical power including the demultiplexer ? adjustable range for offset, full-scale, and sampling instance ? 50 ? differential analog inputs ? 1:4 demultiplexed lvds outputs ? interfaces directly to common fpgas with ddr and qdr modes MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs ________________________________________________________________ maxim integrated products 1 ordering information 19-0795; rev 0; 4/07 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. d = dry pack. evaluation kit available part temp range pin- package pkg code MAX109ehf-d -40? to +85? 256 sbga h256-1 top view a b c d e f g h j k l m n p r t u v w y 1234567891011121314151617181920 MAX109 256-pin super ball-grid array 256-pin sbga package pin configuration
MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs 2 _______________________________________________________________________________________ 50 ? 50 ? 50 ? 8-bit adc core t/h amplifier refin vosadj clkp clkcom input clock buffer clkn gndi tempmon rstinn qdr rstout a[0:7] b[0:7] c[0:7] d[0:7] dor dco demux clock generator ddr delayed reset quantizer clock driver logic clock driver demux clock driver rstinp sampadj inp inn refout reference amplifier 50 ? bandgap reference temperature monitor reset input dual latch demux reset output porta portb portc portd dor dco reset pipeline figure 1. functional diagram of the MAX109
MAX109 absolute maximum ratings dc electrical characteristics (v cc a = v cc i = v cc d = 5v, v cc o = 3.3v, v ee = -5v, gnda = gndi = gndo = gndd = gndr = 0v, vosadj = sampadj = open, digital output pins differential r l = 100 ? . specifications +25? guaranteed by production test, < +25? guaranteed by design and characterization. typical values are at t a = +25?, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc a to gnda ....................................................... -0.3v to +6v v cc d to gndd ....................................................... -0.3v to +6v v cc i to gndi ........................................................... -0.3v to +6v v cc o to gndo ................................................... -0.3v to +3.9v v ee to gndi ............................................................ -6v to +0.3v between grounds (gnda, gndi, gndo, gndd, gndr) ................................................ -0.3v to +0.3v v cc a to v cc d ..................................................... -0.3v to +0.3v v cc a to v cc i ....................................................... -0.3v to +0.3v differential voltage between inp and inn ........................... ?v inp, inn to gndi ................................................................. ?v differential voltage between clkp and clkn..................... ?v clkp, clkn, clkcom to gndi ............................... -3v to +1v digital lvds outputs to gndo .............. -0.3v to (v cc o - 0.3v) refin, refout to gndr ........................-0.3v to (v cc i + 0.3v) refout current ...............................................-100? to +5ma rstinp, rstinn to gnda .....................-0.3v to (v cc o + 0.3v) rstoutp, rstoutn to gndo .............-0.3v to (v cc o + 0.3v) vosadj, sampadj, tempmon to gndi...............................-0.3v to (v cc i + 0.3v) prn, ddr, qdr to gndd.......................-0.3v to (v cc d + 0.3v) delgate0, delgate1 to gnda ...........-0.3v to (v cc a + 0.3v) continuous power dissipation (t a = +70?) 256-ball sbga (derate 74.1mw/? above +70? for a multilayer board) ................................................. 5925.9mw operating temperature range MAX109ehf ...................................................-40? to +85? thermal resistance ja (note 1) .......................................3?/w operating junction temperature.....................................+150? storage temperature range .............................-65? to +150? parameter symbol conditions min typ max units dc accuracy resolution res 8 bits integral nonlinearity (note 2) inl (note 8) -0.8 ?.25 +0.8 lsb differential nonlinearity (note 2) dnl guaranteed no missing codes, t a = +25? (note 8) -0.8 ?.25 +0.8 lsb transfer curve offset (note 2) v os vosadj control input open (note 8) -5.5 0 +5.5 lsb analog inputs (inn, inp) common-mode input-voltage range v cm signal and offset with respect to gndi ? v common-mode rejection ratio (note 3) cmrr 50 db full-scale input range (note 2) v fs v refin = 2.5v 470 500 535 mv p-p input resistance r in 45 50 55 ? input resistance temperature coefficient tc r 150 ppm/? vos adjust control input (vosadj) input resistance (note 4) r vosadj 25 50 75 k ? vosadj = 0v -20 mv input offset voltage v os vosadj = 2.5v 20 mv sample adjust control input (sampadj) input resistance r sampadj 25 50 75 k ? aperture time adjust range t ad sampadj = 0 to 2.5v 30 ps 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs _______________________________________________________________________________________ 3 note 1: thermal resistance is based on a 5in x 5in multilayer board. the data sheet assumes a thermal environment of 3?/w. thermal resistance may be different depending on airflow and heatsink cooling capabilities.
MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units reference input and output (refin, refout) reference output voltage refout 2.460 2.500 2.525 v reference output load regulation ? refout 0 < i source < 2.5ma < 7.5 mv reference input voltage refin 2.500 ? 0.25 v reference input resistance r refin 45 k ? clock inputs (clkp, clkn) clock input amplitude peak-to-peak differential (figure 13b) 200 to 2000 mv clock input common-mode range signal and offset referenced to clkcom -2 to +2 v clock input resistance r clk clkp and clkn to clkcom 45 50 55 ? input resistance temperature coefficient tc r 150 ppm/? cmos control inputs (ddr, qdr, prn, delgate0, delgate1) high-level input voltage v ih threshold voltage = 1.2v 1.4 3.3 v low-level input voltage v il threshold voltage = 1.2v 0.8 v high-level input current i ih v ih = 3.3v 50 ? low-level input current i il v il = 0v -50 ? lvds inputs (rstinp, rstinn) differential input high voltage 0.2 v differential input low voltage -0.2 v minimum common-mode input voltage 1v maximum common-mode input voltage v c c o - 0.15 v temperature measurement output (tempmon) temperature measurement accuracy t (?) = [(v tempmon - v gndi ) x 1303.5] - 371 ? ? output resistance measured between tempmon and gndi 0.725 k ? lvds outputs (porta, portb, portc, portd, dorp, dorn, dcop, dcon, rstoutp, rstoutn) (note 9) differential output voltage v od r load = 100 ? 250 400 mv output offset voltage v os r load = 100 ? 1.10 1.28 v dc electrical characteristics (continued) (v cc a = v cc i = v cc d = 5v, v cc o = 3.3v, v ee = -5v, gnda = gndi = gndo = gndd = gndr = 0v, vosadj = sampadj = open, digital output pins differential r l = 100 ? . specifications +25? guaranteed by production test, < +25? guaranteed by design and characterization. typical values are at t a = +25?, unless otherwise noted.)
MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs _______________________________________________________________________________________ 5 dc electrical characteristics (continued) (v cc a = v cc i = v cc d = 5v, v cc o = 3.3v, v ee = -5v, gnda = gndi = gndo = gndd = gndr = 0v, vosadj = sampadj = open, digital output pins differential r l = 100 ? . specifications +25? guaranteed by production test, < +25? guaranteed by design and characterization. typical values are at t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units power requirements analog supply current iv cc a 556 744 ma positive input supply current iv cc i 125 168 ma negative input supply current i iv ee i 181 240 ma digital supply current iv cc d 291 408 ma output supply current iv cc o 222 300 ma power dissipation p diss 6.50 8.79 w positive power-supply rejection ratio psrrp (note 5) 50 db negative power-supply rejection ratio psrrn v ee = -5.25v to -4.75v 50 db parameter symbol conditions min typ max units analog input analog input full-power bandwidth (note 6) bw -3db 2.8 ghz gain flatness gf 1100mhz to 2200mhz ?.3 db dynamic specifications snr 300 f in = 300mhz, f clk = 2.2gsps 44.6 snr 1000 f in = 1000mhz, f clk = 2.2gsps (note 8) 43.6 44.5 snr 1600 f in = 1600mhz, f clk = 2.2gsps (note 8) 42.2 44.0 snr 2500 f in = 2500mhz, f clk = 2.2gsps 42.9 snr 500 f in = 500mhz, f clk = 2.5gsps 44.4 signal-to-noise ratio snr 1600 f in = 1600mhz, f clk = 2.5gsps 44.0 db thd 300 f in = 300mhz, f clk = 2.2gsps -55.6 thd 1000 f in = 1000mhz, f clk = 2.2gsps (note 8) -48.5 -42.5 thd 1600 f in = 1600mhz, f clk = 2.2gsps (note 8) -46.6 -39.6 thd 2500 f in = 2500mhz, f clk = 2.2gsps -43.7 thd 500 f in = 500mhz, f clk = 2.5gsps -49.0 total h ar m oni c d i stor ti on ( n ote 7) thd 1600 f in = 1600mhz, f clk = 2.5gsps -43.1 dbc ac electrical characteristics (v cc a = v cc i = v cc d = 5v, v cc o = 3.3v, v ee = -5v, gnda = gndi = gndd = gndo = gndr = 0v, f clk = 2.2gsps, analog input amplitude at -1dbfs differential, clock input amplitude 400mv p-p differential, digital output pins differential r l = 100 ? . typical values are at t a = +25?, unless otherwise noted.)
MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs 6 _______________________________________________________________________________________ ac electrical characteristics (continued) (v cc a = v cc i = v cc d = 5v, v cc o = 3.3v, v ee = -5v, gnda = gndi = gndd = gndo = gndr = 0v, f clk = 2.2gsps, analog input amplitude at -1dbfs differential, clock input amplitude 400mv p-p differential, digital output pins differential r l = 100 ? . typical values are at t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units sfdr 300 f in = 300mhz, f clk = 2.2gsps 61.7 sfdr 1000 f in = 1000mhz, f clk = 2.2gsps (note 8) 44.4 51.1 sfdr 1600 f in = 1600mhz, f clk = 2.2gsps (note 8) 43.7 50.3 sfdr 2500 f in = 2500mhz, f clk = 2.2gsps 45.0 sfdr 500 f in = 500mhz, f clk = 2.5gsps 53.7 spurious free dynamic range sfdr 1600 f in = 1600mhz, f clk = 2.5gsps 44.6 dbc sinad 300 f in = 300mhz, f clk = 2.2gsps 44.1 sinad 1000 f in = 1000mhz, f clk = 2.2gsps (note 8) 40.4 43.1 sinad 1600 f in = 1600mhz, f clk = 2.2gsps (note 8) 37.9 42.1 sinad 2500 f in = 2500mhz, f clk = 2.2gsps 40.1 sinad 500 f in = 500mhz, f clk = 2.5gsps 43.1 signal-to-noise-plus-distortion ratio sinad 1600 f in = 1600mhz, f clk = 2.5gsps 40.5 db third-order intermodulation im3 f in1 = 1590mhz, f in2 = 1610mhz at -7dbfs -60 dbc metastability probability 10 -14 timing characteristics maximum sample rate f clk ( max ) 2.2 gsps clock pulse-width low t pwl t clk = t pwl + t pwh (note 8) 180 ps clock pulse-width high t pwh t clk = t pwl + t pwh (note 8) 180 ps aperture delay t ad 200 ps aperture jitter t aj 0.2 ps reset input data setup time t su (note 8) 300 ps reset input data hold time t hd (note 8) 250 ps t pd1 dco = f clk / 4, clk fall to dco rise time 1.6 t pd1ddr dco = f clk / 8, ddr mode, clk fall to dco rise time 1.6 clk-to-dco propagation delay t pd1qdr dco = f clk / 16, qdr mode, clk fall to dco rise time 1.6 ns t pd2 dco = f clk / 4, dco rise to data transition (note 8) -520 +520 t pd2ddr dco = f clk / 8, ddr mode, dco rise to data transition (note 8) -520 + 2t clk 2t clk 520 + 2t clk dco-to-data propagation delay t pd2qdr dco = f clk / 16, qdr mode, dco rise to data transition (note 8) -520 + 2t clk 2t clk 520 + 2t clk ps dco duty cycle clock mode independent 45 to 55 %
MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs _______________________________________________________________________________________ 7 ac electrical characteristics (continued) (v cc a = v cc i = v cc d = 5v, v cc o = 3.3v, v ee = -5v, gnda = gndi = gndd = gndo = gndr = 0v, f clk = 2.2gsps, analog input amplitude at -1dbfs differential, clock input amplitude 400mv p-p differential, digital output pins differential r l = 100 ? . typical values are at t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units lvds output rise time t rdata 20% to 80%, c l < 2pf 500 ps lvds output fall time t fdata 20% to 80%, c l < 2pf 500 ps lvds differential skew t skew1 any two lvds output signals, except dco <100 ps portd data pipeline delay t pdd 7.5 clock cycles portc data pipeline delay t pdc 8.5 clock cycles portb data pipeline delay t pdb 9.5 clock cycles porta data pipeline delay t pda 10.5 clock cycles note 2: static linearity and offset parameters are computed from a best-fit straight line through the code transition points. the full- scale range (fsr) is defined as 255 x slope of the line where the slope of the line is determined by the end-point code tran- sitions. when the analog input voltage exceeds positive fsr, the output code is 11111111; when the analog input voltage is beyond the negative fsr, the output code is 00000000. note 3: common-mode rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in the common-mode voltage, expressed in db. note 4: the offset-adjust control input is tied to an internal 1.25v reference level through a resistor. note 5: measured with the positive supplies tied to the same potential, v cc a = v cc d = v cc i. v cc varies from 4.75v to 5.25v. note 6: to achieve 2.8ghz full-power bandwidth, careful board layout techniques are required. note 7: the total harmonic distortion (thd) is computed from the second through the 15th harmonics. note 8: guaranteed by design and characterization. note 9: rstoutp/rstoutn are tested for functionality. typical operating characteristics (v cc a = v cc i = v cc d = 5v, v cc o = 3.3v, v ee = -5v, gnda = gndi = gndd = gndo = gndr = 0v, f clk = 2.21184gsps, analog input amplitude at -1dbfs differential, clock input amplitude 10dbm differential, digital output pins differential r l = 100 ? . typical values are at t j = +105?, unless otherwise noted.) -90 -70 -80 -40 -50 -60 -10 -20 -30 0 fft plot (16,384-point data record) MAX109 toc02 amplitude (db) f clk = 2.21184ghz f in = 300.105mhz a in = -1.034dbfs snr = 45.1db sinad = 44.8db thd = -56.2dbc sfdr = 62.4dbc hd2 = -64.4dbc hd3 = -62.7dbc 0 552.96 276.48 829.44 1105.92 414.72 138.24 691.20 967.68 analog input frequency (mhz) -90 -70 -80 -40 -50 -60 -10 -20 -30 0 0 552.96 276.48 829.44 1105.92 414.72 138.24 691.20 967.68 fft plot (16,384-point data record) MAX109 toc01 analog input frequency (mhz) amplitude (db) f clk = 2.21184ghz f in = 98.145mhz a in = -0.975dbfs snr = 45.2db sinad = 44.8db thd = -55.7dbc sfdr = 57.2dbc hd2 = -69.6dbc hd3 = -57.2dbc -90 -70 -80 -40 -50 -60 -10 -20 -30 0 fft plot (16,384-point data record) MAX109 toc03 amplitude (db) f clk = 2.21184ghz f in = 999.135mhz a in = -1.059dbfs snr = 44.5db sinad = 43.3db thd = -49.5dbc sfdr = 52.1dbc hd2 = -57.3dbc hd3 = -52.1dbc 0 552.96 276.48 829.44 1105.92 414.72 138.24 691.20 967.68 analog input frequency (mhz)
MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs 8 _______________________________________________________________________________________ -90 -70 -80 -40 -50 -60 -10 -20 -30 0 fft plot (16,384-point data record) MAX109 toc05 amplitude (db) f clk = 2.49856ghz f in = 1599.268mhz a in = -1.059dbfs snr = 44.1db sinad = 41.2db thd = -44.4dbc sfdr = 46.1dbc hd2 = -50.1dbc hd3 = -46.1dbc 0 624.64 312.32 936.96 1249.28 468.48 156.16 780.8 1098.12 analog input frequency (mhz) -90 -70 -80 -40 -50 -60 -10 -20 -30 0 ttimd plot (16,384-point data record) MAX109 toc06 amplitude (db) f clk = 2.21184ghz f in1 = 1590.165mhz f in2 = 1610.415mhz a in1 = a in2 = -7.13dbfs im3 = -60.8dbc 0 552.96 276.48 829.44 1105.92 414.72 138.24 691.20 967.68 analog input frequency (mhz) 2f in2 - f in1 2f in1 - f in2 snr, sinad vs. analog input frequency (f clk = 2.21184gsps, a in = -1dbfs) f in (mhz) snr, sinad (db) MAX109 toc07 0 500 1000 1500 2000 2500 30 34 38 42 46 50 sinad snr enob vs. analog input frequency (f clk = 2.21184gsps, a in = -1dbfs) f in (mhz) enob (bits) MAX109 toc08 0 500 1000 1500 2000 2500 5.0 5.5 6.0 6.5 7.0 7.5 8.0 -thd, sfdr vs. analog input frequency (f clk = 2.21184gsps, a in = -1dbfs) f in (mhz) -thd, sfdr (dbc) MAX109 toc09 0 500 1000 1500 2000 2500 35 40 45 50 55 60 65 sfdr -thd hd2, hd3 vs. analog input frequency (f clk = 2.21184gsps, a in = -1dbfs) f in (mhz) hd2 , hd3 (db c ) MAX109 toc10 0 500 1000 1500 2000 2500 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 hd3 hd2 snr, sinad vs. analog input frequency (f clk = 2.49856gsps, a in = -1dbfs) f in (mhz) snr, sinad (db) MAX109 toc11 0 500 1000 1500 2000 2500 30 34 38 42 46 50 snr sinad enob vs. analog input frequency (f clk = 2.49856gsps, a in = -1dbfs) f in (mhz) enob (bits) MAX109 toc12 0 500 1000 1500 2000 2500 5.0 5.5 6.0 6.5 7.0 7.5 8.0 typical operating characteristics (continued) (v cc a = v cc i = v cc d = 5v, v cc o = 3.3v, v ee = -5v, gnda = gndi = gndd = gndo = gndr = 0v, f clk = 2.21184gsps, analog input amplitude at -1dbfs differential, clock input amplitude 10dbm differential, digital output pins differential r l = 100 ? . typical values are at t j = +105?, unless otherwise noted.) -90 -70 -80 -40 -50 -60 -10 -20 -30 0 fft plot (16,384-point data record) MAX109 toc04 amplitude (db) f clk = 2.21184ghz f in = 1600.155mhz a in = -0.992dbfs snr = 44.2db sinad = 42.6db thd = -47.5dbc sfdr = 51.1dbc hd2 = -51.1dbc hd3 = -52.1dbc 0 552.96 276.48 829.44 1105.92 414.72 138.24 691.20 967.68 analog input frequency (mhz)
MAX109 typical operating characteristics (continued) (v cc a = v cc i = v cc d = 5v, v cc o = 3.3v, v ee = -5v, gnda = gndi = gndd = gndo = gndr = 0v, f clk = 2.21184gsps, analog input amplitude at -1dbfs differential, clock input amplitude 10dbm differential, digital output pins differential r l = 100 ? . typical values are at t j = +105?, unless otherwise noted.) 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs _______________________________________________________________________________________ 9 hd2, hd3 vs. analog input frequency (f clk = 2.49865gsps, a in = -1dbfs) f in (mhz) hd2, hd3 (dbc) MAX109 toc14 0 500 1000 1500 2000 2500 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 hd3 hd2 snr, sinad vs. analog input amplitude (f clk = 2.21184gsps, f in = 1600.1550mhz) a in (dbfs) snr, sinad (db) MAX109 toc15 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 0 5 10 15 20 25 30 35 40 45 sinad snr enob vs. analog input amplitude (f clk = 2.21184gsps, f in = 1600.1550mhz) a in (dbfs) enob (bits) MAX109 to16 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 -thd, sfdr vs. analog input amplitude (f clk = 2.21184gsps, f in = 1600.1550mhz) a in (dbfs) -thd, sfdr (dbc) MAX109 toc17 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 20 25 30 35 40 45 50 55 60 sfdr -thd hd2, hd3 vs. analog input amplitude (f clk = 2.21184gsps, f in = 1600.1550mhz) a in (dbfs) hd2, hd3 (dbc) MAX109 toc18 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 hd3 hd2 snr, sinad vs. clock speed (f in = 1600mhz, a in = -1dbfs) f clk (mhz) snr, sinad (db) MAX109 toc19 500 750 1000 1250 1500 1750 2000 2250 2500 30 34 38 42 46 50 snr sinad enob vs. clock speed (f in = 1600mhz, a in = -1dbfs) f clk (mhz) enob (bits) MAX109 toc20 500 750 1000 1250 1500 1750 2000 2250 2500 5.0 5.5 6.0 6.5 7.0 7.5 8.0 -thd, sfdr vs. clock speed (f in = 1600mhz, a in = -1dbfs) f clk (mhz) -thd, sfdr (dbc) MAX109 toc21 500 750 1000 1250 1500 1750 2000 2250 2500 35 40 45 50 55 60 sfdr -thd -thd, sfdr vs. analog input frequency (f clk = 2.49856gsps, a in = -1dbfs) f in (mhz) -thd, sfdr (dbc) MAX109 toc13 0 500 1000 1500 2000 2500 35 40 45 50 55 60 65 sfdr -thd
MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs 10 ______________________________________________________________________________________ snr, sinad vs. v cc a/v cc i (f in = 1600.1550mhz, a in = -1dbfs) v cc a/v cc i (v) snr, sinad (db) MAX109 toc23 4.75 4.85 4.95 5.05 5.15 5.25 36 38 40 42 44 46 48 50 snr v cc a and v cc i connected together v cc d = 5v v cc o = 3.3v v ee = -5v sinad -thd, sfdr vs. v cc a/v cc i (f in = 1600.1550mhz, a in = -1dbfs) v cc a/v cc i (v) -thd, sfdr (dbc) MAX109 toc24 4.75 4.85 4.95 5.05 5.15 5.25 44 45 46 47 48 49 50 51 52 53 v cc d = 5v v cc o = 3.3v v ee = -5v sfdr -thd v cca and v cc i connected together snr, sinad vs. v cc d (f in = 1600.1550mhz, a in = -1dbfs) v cc d (v) snr, sinad (db) MAX109 toc25 4.75 4.85 4.95 5.05 5.15 5.25 36 38 40 42 44 46 48 50 v cc a = v cc i = 5v v cc o = 3.3v v ee = -5v sinad snr -thd, sfdr vs. v cc d (f in = 1600.1550mhz, a in = -1dbfs) v cc d (v) -thd, sfdr (dbc) MAX109 toc26 4.75 4.85 4.95 5.05 5.15 5.25 44 45 46 47 48 49 50 51 52 53 v cc a = v cc i = 5v v cc o = 3.3v v ee = -5v sfdr -thd snr, sinad vs. v ee (f in = 1600.1550mhz, a in = -1dbfs) v ee (v) snr, sinad (db) MAX109 toc27 -5.25 -5.15 -5.05 -4.95 -4.85 -4.75 36 38 40 42 44 46 48 50 v cc a = v cc i = 5v v cc d = 5v v cc o = 3.3v sinad snr -thd, sfdr vs. v ee (f in = 1600.1550mhz, a in = -1dbfs) v ee (v) -thd, sfdr (dbc) MAX109 toc28 -5.25 -5.15 -5.05 -4.95 -4.85 -4.75 44 45 46 47 48 49 50 51 52 53 v cc a = v cc i = 5v v cc d = 5v v cc o = 3.3v sfdr -thd 0 96 128 32 64 160 192 224 256 integral nonlinearity vs. digital output code (262,144-point data record) MAX109 toc29 digital output code inl (lsb) -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 96 128 32 64 160 192 224 256 differential nonlinearity vs. digital output code (262,144-point data record) MAX109 toc30 digital output code dnl (lsb) -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 typical operating characteristics (continued) (v cc a = v cc i = v cc d = 5v, v cc o = 3.3v, v ee = -5v, gnda = gndi = gndd = gndo = gndr = 0v, f clk = 2.21184gsps, analog input amplitude at -1dbfs differential, clock input amplitude 10dbm differential, digital output pins differential r l = 100 ? . typical values are at t j = +105?, unless otherwise noted.) hd2, hd3 vs. clock speed (f in = 1600mhz, a in = -1dbfs) f clk (mhz) hd2, hd3 (dbc) MAX109 toc22 500 750 1000 1250 1500 1750 2000 2250 2500 -75 -70 -65 -60 -55 -50 -45 -40 hd3 hd2
MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs ______________________________________________________________________________________ 11 small-signal input bandwidth vs. analog input frequency (a in = -20dbfs) analog input frequency (mhz) gain (db) MAX109 toc32 -6 -5 -4 -3 -2 -1 0 1 10 100 1000 10,000 reference voltage vs. v cc a/v cc i v cc a/v cc i (v) v refout (v) MAX109 toc33 4.75 4.85 4.95 5.05 5.15 5.25 2.4925 2.4935 2.4945 2.4955 2.4965 2.4975 2.4985 2.4995 v cc a and v cc i connected together v cc o = 3.3v v cc d = 5v v ee = -5v analog/digital power dissipation vs. v cc a/v cc i/v cc d/-v ee (f in = 1600.1550mhz, a in = -1dbfs) v cc a/v cc i/v cc d/-v ee (v) power dissipation (mw) MAX109 toc34 4.75 4.85 4.95 5.05 5.15 5.25 5300 5600 5900 6200 6500 6800 v cc o = 3.3v v cc a = v cc i = v cc d = 4.75v to 5v v ee = -4.75v to -5.25v output driver power dissipation vs. v cc o (f in = 1600.1550mhz, a in = -1dbfs) v cc o (v) power dissipation (mw) MAX109 toc35 3.0 3.1 3.2 3.3 3.4 3.5 3.6 650 700 750 800 850 900 v cc o = 3v to 3.6v v cc a = v cc i = v cc d = 5v v ee = -5v snr, sinad vs. temperature (f in = 1600.1550mhz, a in = -1dbfs) snr, sinad (db) MAX109 toc36 -40 -15 10 35 60 85 [-22.1] [7.5] [37.1] [66.7] [96.3] [125.9] 35 37 39 41 43 45 snr sinad temperature ( c) [die temperature ( c)] enob vs. temperature (f in = 1600.1550mhz, a in = -1dbfs) temperature ( c) [die temperature ( c)] enob (bits) MAX109 toc37 -40 -15 10 35 60 85 5.50 5.75 6.00 6.25 6.50 6.75 7.00 7.25 7.50 [-22.1] [7.5] [37.1] [66.7] [96.3] [125.9] -thd, sfdr vs. temperature (f in = 1600.1550mhz, a in = -1dbfs) -thd, sfdr (dbc) MAX109 toc38 -40 -15 10 35 60 85 38 40 42 44 46 48 50 52 54 temperature ( c) [die temperature ( c)] [-22.1] [7.5] [37.1] [66.7] [96.3] [125.9] sfdr -thd hd2, hd3 vs. temperature (f in = 1600.1550mhz, a in = -1dbfs) hd2, hd3 (dbc) MAX109 toc39 -40 -15 10 35 60 85 -56 -54 -52 -50 -48 -46 -44 temperature ( c) [die temperature ( c)] [-22.1] [7.5] [37.1] [66.7] [96.3] [125.9] hd2 hd3 full-power input bandwidth vs. analog input frequency (a in = -1dbfs) analog input frequency (mhz) gain (db) MAX109 toc31 -6 -5 -4 -3 -2 -1 0 1 10 100 1000 10,000 typical operating characteristics (continued) (v cc a = v cc i = v cc d = 5v, v cc o = 3.3v, v ee = -5v, gnda = gndi = gndd = gndo = gndr = 0v, f clk = 2.21184gsps, analog input amplitude at -1dbfs differential, clock input amplitude 10dbm differential, digital output pins differential r l = 100 ? . typical values are at t j = +105?, unless otherwise noted.)
MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs 12 ______________________________________________________________________________________ pin name 12 ______________________________________________________________________________________ pin description pin name function a1, a2, b1, b2, c1?5, d5, l1?4, u5, v1?4, w1, w2, y1, y2 v cc o lvds output power supply. accepts an input-voltage range of 3.3v ?0%. a3, a4, b3, b4, d1?4, k1?4, u1?4, w3, w4, y3, y4 gndo lvds output ground. ground connection for lvds output drivers. a9, b9, c10, d10, u10, v10, w10, y10 v cc d digital logic power supply. accepts an input-voltage range of 5v ?%. a10, b10, c11, d11, u11, v11, w11, y11 gndd digital ground. ground connection for digital logic circuitry. a11, a19, b11, b18, c12, c18, d12, d18, e17, u17, v17, w17, y17, u12, v12, w12, y12 v cc a analog supply voltage for comparator array. accepts an input-voltage range of 5v ?%. a12, a18, b12, b13, b17, c13, c17, d13, d17, u13, u16, v13, v16, w13, w16, y13, y16 gnda analog ground. ground connection for comparator array. h17?20, p17?20, u15, v15, w15, y15 v cc i analog supply voltage. analog power supply (positive rail) for t/h amplifier. accepts an input- voltage range of 5v ?%. e18, f17?20, j17, j18, j19, n17, n18, n19, t17?20, u18 v ee negative power supply. analog power supply (negative rail) for the t/h amplifier. accepts an input-voltage range of -5v ?%. d 19, d 20, e 19, e 20, g17g20, j20, k17, k18, k19, l17l20, m 17, m 18, m 19, n 20, r17r20, u 14, u 19, u 20, v 14, v 19, v 20, w14, y 14 gndi analog ground. ground connection for the t/h amplifier.
MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs ______________________________________________________________________________________ 13 pin name ______________________________________________________________________________________ 13 pin description (continued) pin name function a14 clkp true/positive sampling clock input. positive terminal for differential input configuration. a16 clkn complementary/negative sampling clock input. negative terminal for differential input configuration. a13, a15, a17, b14, b15, b16, c14, c15, c16, d14, d15, d16 clkcom 50 ? clock termination return b20 sampadj sampling point adjustment input. allows the user to adjust the sampling event by applying a voltage between 0 to 2.5v to this input. b19 delgate1 timing delay adjustment. coarse (msb) adjustment for the timing between t/h amplifier and quantizer. c19 delgate0 timing delay adjustment. coarse (lsb) adjustment for the timing between t/h amplifier and quantizer. y20 refin reference voltage input. for applications requiring improved gain performance and reference- voltage adjustability, allows the user to utilize the refin input by applying a more accurate and adjustable reference source. this input accepts an input-voltage range of 2.5v ?0%. y19 refout internal reference output. connect to refin, if using the internal 2.5v bandgap reference. v18, w18, y18 gndr bandgap reference ground. ground connection for the internal bandgap reference and its related circuitry. m20 inp true/positive analog input terminal. for single-ended signals, apply signal to inp and reverse- terminate inn to gndi with a 50 ? resistor. k20 inn c om p l em entar y/n eg ati ve anal og inp ut ter m i nal . for si ng l ed - end ed si g nal s, r ever se- ter m i nate in n to gn d i w i th a 50 ? r esi stor and ap p l y the si g nal d i r ectl y to in p . w20 vosadj analog voltage input to adjust the converter offset. this input accepts an input-voltage range of 0 to 2.5v allowing the offset to be adjusted at roughly ?0 lsb. m4 dorp true/positive lvds data-overrange output bit. this output flags over- and under-range conditions of the data converter. m3 dorn complementary/negative lvds data-overrange output bit. this output flags over- and under- range conditions on the data converter. m2 dcop true/positive lvds data clock output. synchronize user-supplied data-capture board or data- acquisition system to this clock. m1 dcon complementary/negative lvds data clock output. synchronize user-supplied data-capture board or data-acquisition system to this clock.
MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs 14 ______________________________________________________________________________________ pin description (continued) pin name function y5 qdr quad data rate input (cmos). connect to gndd for the default data rate to be applied. connect to v cc d to achieve four times the specified data rate. w5 ddr double data rate input (cmos). connect to gndd for the standard data rate to be applied. connect to v cc d to achieve two times the specified data rate. v5 prn pseudorandom number generator enable input (cmos). when enabled, pseudorandom patterns appear on all four lvds output ports (porta, portb, portc, and portd). d9 rstinp true/positive reset input c9 rstinn complementary/negative reset input b5 rstoutp true/positive lvds reset output a5 rstoutn complementary lvds reset output b8 d7p true/positive output bit d7p, portd, bit 7 a8 d7n complementary/negative output bit d7n, portd, bit 7 b6 d6p true/positive output bit d6p, portd, bit 6 a6 d6n complementary/negative output bit d6n, portd, bit 6 f2 d5p true/positive output bit d5p, portd, bit 5 f1 d5n complementary/negative output bit d5n, portd, bit 5 h2 d4p true/positive output bit d4p, portd, bit 4 h1 d4n complementary/negative output bit d4n, portd, bit 4 n2 d3p true/positive output bit d3p, portd, bit 3 n1 d3n complementary/negative output bit d3n, portd, bit 3 r2 d2p true/positive output bit d2p, portd, bit 2 r1 d2n complementary/negative output bit d2n, portd, bit 2 w6 d1p true/positive output bit d1p, portd, bit 1 y6 d1n complementary/negative output bit d1n, portd, bit 1 w8 d0p true/positive output bit d0p, portd, bit 0 y8 d0n complementary/negative output bit, d0n, portd, bit 0 d8 c7p true/positive output bit c7p, portc, bit 7 c8 c7n complementary/negative output bit c7n, portc, bit 7 d6 c6p true/positive output bit c6p, portc, bit 6 c6 c6n complementary/negative output bit c6n, portc, bit 6 f4 c5p true/positive output bit c5p, portc, bit 5 f3 c5n complementary/negative output bit c5n, portc, bit 5 h4 c4p true/positive output bit c4p, portc, bit 4 h3 c4n complementary/negative output bit c4n, portc, bit 4 n4 c3p true/positive output bit c3p, portc, bit 3 n3 c3n complementary/negative output bit c3n, portc, bit 3 r4 c2p true/positive output bit c2p, portc, bit 2
MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs ______________________________________________________________________________________ 15 pin description (continued) pin name function r3 c2n complementary/negative output bit c2n, portc, bit 2 u6 c1p true/positive output bit c1p, portc, bit 1 v6 c1n complementary/negative output bit c1n, portc, bit 1 u8 c0p true/positive output bit c0p, portc, bit 0 v8 c0n complementary/negative output bit c0n, portc, bit 0 b7 b7p true/positive output bit b7p, portb, bit 7 a7 b7n complementary/negative output bit b7n, portb, bit 7 e2 b6p true/positive output bit b6p, portb, bit, 6 e1 b6n complementary/negative output bit b6n, portb, bit 6 g2 b5p true/positive output bit b5p, portb, bit 5 g1 b5n complementary/negative output bit b5n, portb, bit 5 j2 b4p true/positive output bit b4p, portb, bit 4 j1 b4n complementary/negative output bit b4n, portb, bit 4 p2 b3p true/positive output bit b3p, portb, bit 3 p1 b3n complementary/negative output bit b3n, portb, bit 3 t2 b2p true/positive output bit b2p, portb, bit 2 t1 b2n complementary/negative output bit b2n, portb, bit 2 w7 b1p true/positive output bit b1p, portb, bit 1 y7 b1n complementary/negative output bit b1n, portb, bit 1 w9 b0p true/positive output bit b0p, portb, bit 0 y9 b0n complementary/negative output bit b0n, portb, bit 0 d7 a7p true/positive output bit a7p, porta, bit 7 c7 a7n complementary/negative output bit a7n, porta, bit 7 e4 a6p true/positive output bit a6p, porta, bit 6 e3 a6n complementary/negative output bit a6n, porta, bit 6 g4 a5p true/positive output bit a5p, porta, bit 5 g3 a5n complementary/negative output bit a5n, porta, bit 5 j4 a4p true/positive output bit a4p, porta, bit 4 j3 a4n complementary/negative output bit a4n, porta, bit 4 p4 a3p true/positive output bit a3p, porta, bit 3 p3 a3n complementary/negative output bit a3n, porta, bit 3 t4 a2p true/positive output bit a2p, porta, bit 2 t3 a2n complementary/negative output bit a2n, porta, bit 2
MAX109 detailed description the MAX109 is an 8-bit, 2.2gsps flash analog-to-digital converter (adc) with an on-chip t/h amplifier and 1:4 demultiplexed high-speed lvds outputs. the adc (figure 1) employs a fully differential 8-bit quantizer and a unique encoding scheme to limit metastable states and ensures no error exceeds a maximum of 1 lsb. an integrated 1:4 output demultiplexer simplifies inter- facing to the part by reducing the output data rate to one-quarter the sampling clock rate. this demultiplexer circuit has integrated reset capabilities that allow multi- ple MAX109 converters to be time-interleaved to achieve higher effective sampling rates. when clocked at 2.2gsps, the MAX109 provides a typical effective number of bits (enob) of 6.9 bits at an analog input frequency of 1600mhz. the MAX109 analog input is designed for both differential and single-ended use with a 500mv p-p full-scale input range. in addition, this fast adc features an on-chip 2.5v precision bandgap reference. in order to improve the MAX109 gain error further, an exter- nal reference may be used (see the internal reference section). principle of operation the architecture of the MAX109 provides the fastest multibit conversion of all common integrated adc designs. the key to its architecture is an innovative, high-performance comparator design. the MAX109 quantizer and its encoding logic translate the compara- tor outputs into a parallel 8-bit output code and pass the binary code on to the 1:4 demultiplexer. four sepa- rate ports (porta, portb, portc, and portd) output true lvds data at speeds of up to 550msps per port (depending on how the demultiplexer section is set on the MAX109). the ideal transfer function appears in figure 2. on-chip track/hold amplifier as with all adcs, if the input waveform is changing rapidly during conversion, enob and signal-to-noise ratio (snr) specifications will degrade. the MAX109? on-chip, wide-bandwidth (2.8ghz) t/h amplifier reduces this effect and increases the enob perfor- mance significantly, allowing precise capture of fast- changing analog data at high conversion rates. the t/h amplifier accepts and buffers both dc- and ac-coupled analog input signals and allows a full-scale signal input range of 500mv p-p . the t/h amplifier? dif- ferential 50 ? input termination simplifies interfacing to the MAX109 with controlled impedance lines. figure 3 shows a simplified diagram of the t/h amplifier stage internal to the MAX109. 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs 16 ______________________________________________________________________________________ pin description (continued) pin name function u7 a1p true/positive output bit a1p, porta, bit 1 v7 a1n complementary/negative output bit a1n, porta, bit 1 u9 a0p true/positive output bit a0p, porta, bit 0 v9 a0n complementary/negative output bit a0n, porta, bit 0 w19 tempmon temp er atur e m oni tor outp ut. resul ting outp ut vol tage cor r esp onds to d i e temp er atur e. a20, c20 t.p. test point. do not connect. (-fs + 1 lsb) 0 +fs (+fs - 1 lsb) 255 255 254 129 128 127 126 3 2 1 0 analog input overrange + overrange digital output figure 2. ideal transfer function
MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs ______________________________________________________________________________________ 17 aperture width, delay, and jitter are parameters that affect the dynamic performance of high-speed convert- ers. aperture jitter, in particular, directly influences snr and limits the maximum slew rate (dv/dt) that can be digitized without contributing significant errors. the MAX109? innovative t/h amplifier design limits aper- ture jitter typically to 0.2ps. aperture width, aperture jitter, and aperture delay aperture width (t aw ) is the time the t/h circuit requires to disconnect the hold capacitor from the input circuit (e.g., to turn off the sampling bridge and put the t/h unit in hold mode). aperture jitter (t aj ) is the sample-to- sample variation in the time between the samples. aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample event is occurring (figure 4). clock system the MAX109 clock signals are terminated with 50 ? to the clkcom pin. the clock system provides clock sig- nals, t/h amplifier, quantizer, and all back-end digital blocks. the MAX109 also produces a digitized output clock for synchronization with external fpga or data- capture devices. note that there is a 1.6ns delay between the clock input (clkp/clkn) and its digitized output representation (dcop/dcon). sampling point adjustment (sampadj) the proper sampling point can be adjusted by utilizing sampadj as the control line. sampadj accepts an input-voltage range of 0 to 2.5v, correlating with up to 32ps timing adjustment. the nominal open-circuit volt- age corresponds to the minimum sampling delay. with an input resistance r sampadj of typically 50k ? , this pin can be adjusted externally with a 10k ? potentiome- ter connected between refout and gndi to adjust for the proper sampling point. t/h amplifier to quantizer capture point adjustment (delgate0, delgate1) another important feature of the MAX109, is the selec- tion of the proper quantizer capture point between the t/h amplifier and the adc core. depending on the selected sampling speed for the application, two con- trol lines can be utilized to set the proper capture point between these two circuits. delgate0 (lsb) and del- gate1 (msb) set the coarse timing of the proper cap- ture point. using these control lines allow the user to adjust the time after which the quantizer latches held data from the t/h amplifier between 25ps and 50ps (table 1). this timing feature enables the MAX109 t/h amplifier to settle its output properly before the quantiz- er captures and digitizes the data, thereby achieving the best dynamic performance for any application. to comparators to comparators buffer amplifier input amplifier clock splitter simplified diagram (input esd protection not shown). gndi t/h 50 ? 50 ? inp inn gndi c hold 50 ? 50 ? clkp clkn clkcom figure 3. internal structure of the 3.2ghz t/h amplifier hold clkp analog input sampled data (t/h) t/h t aw t ad t aj track track aperture delay (t ad ) aperture width (t aw ) aperture jitter (t aj ) clkn figure 4. t/h aperture timing
MAX109 internal reference the MAX109 features an on-chip 2.5v precision bandgap reference used to generate the full-scale range for the data converter. connecting refin with refout applies the reference output to the positive input of the reference buffer. the buffer? negative input is internally connected to gndr. it is recommended that gndr be connected to gndi on the user? appli- cation board. if required, refout can source up to 2.5ma to supply other external devices. additionally, an adjustable external reference can be used to adjust the adc? full- scale range. to use an external reference supply, con- nect a high-precision bandgap reference to the refin pin and leave the refout pin floating. refin has a typical input resistance r refin of 5k ? and accepts input voltages of 2.5v ?0%. digital lvds outputs the MAX109 provides data in offset binary format to differential lvds outputs on four output ports (porta, portb, portc, and portd). a simplified circuit schematic of the lvds output cells is shown in figure 5. all lvds outputs are powered from the output driver supply v cc o, which can be operated at 3.3v ?0%. the MAX109 lvds outputs provide a differential output- voltage swing of 600mv p-p with a common-mode volt- age of approximately 1.2v, and must be differentially terminated at the far end of each transmission line pair (true and complementary) with 100 ? . data out-of-range operation (dorp, dorn) a single differential output pair (dorp, dorn) is pro- vided to flag an out-of-range condition, if the applied signal is outside the allowable input range, where out- of-range is above positive full scale (+fs) or below negative full scale (-fs). the dorp/dorn transitions high/low whenever any of the four output ports (porta, portb, portc, and portd) display out-of-range data. dorp/dorn features the same latency as the adc output data and is demultiplexed in a similar fashion, so that this out-of-range signal and the data samples are time-aligned. demultiplexer operation the MAX109? internal 1:4 demultiplexer spreads the adc core? 8-bit data across 32 true lvds outputs and allows for easy data capture in three different modes. two ttl/cmos-compatible inputs are utilized to create the different modes: sdr (standard data rate), ddr 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs 18 ______________________________________________________________________________________ table 1. timing adjustments for t/h amplifier and quantizer delgate1 delgate0 t im e del a y b et ween t /h a n d q u a n t iz er recommended for clock speeds of 0 1 25ps f clk = 2.2gsps to 2.5gsps 1 0 50ps f clk = 1.75gsps to 2.2gsps table 2. data rate selection for demultiplexer operation ddr qdr demultiplexer operation dco speed 0x sdr mode, porta, portb, portc, and portd enabled, 550msps per port f clk / 4 10 ddr mode, porta, portb, portc, and portd enabled, 550msps per port f clk / 8 11 qdr mode, porta, portb, portc, and portd enabled, 550msps per port f c lk / 16 aop?7p bop?7p cop?7p dop?7p dcop rstoutp aon?7n bon?7n con?7n don?7n dcon rstoutn cmfb: common-mode feedback cmfb gndo gndo v cc o v cc o figure 5. simplified lvds output circuitry x = do not care.
(double data rate), and qdr (quadruple data rate). setting these two bits for different modes allows the user to update and process the outputs at one-quarter (sdr mode), one-eighth (ddr mode), or one-sixteenth (qdr mode) the sampling clock (table 2), relaxing the need for an ultra-fast fpga or data-capture interface. data is presented on all four ports of the converter- demultiplexer circuit outputs. note that there is a data latency between the sampled data and each of the out- put ports. the data latency is 10.5 clock cycles for porta, 9.5 clock cycles for portb, 8.5 clock cycles for portc, and 7.5 clock cycles for portd. this holds true for all demultiplexer modes. figures 6, 7, and 8 display the demultiplexer timing for f clk / 4, f clk / 8, and f clk / 16 modes. pseudorandom number (prn) generator the MAX109 features a prn generator that enables the user to test the demultiplexed digital outputs at full clock speed and with a known test pattern. the prn generator is a combination of shift register and feed- back logic with 255 states. when prn is high, the inter- MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs ______________________________________________________________________________________ 19 table 3. pseudorandom number generator patterns code output prn pattern 1 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 0 3 0 0 0 0 0 1 0 0 4 0 0 0 0 1 0 0 0 5 0 0 0 1 0 0 0 1 6 0 0 1 0 0 0 1 1 7 0 1 0 0 0 1 1 1 8 1 0 0 0 1 1 1 0 9 0 0 0 1 1 1 0 0 10 0 0 1 1 1 0 0 0 250 0 0 1 1 0 1 0 0 251 0 1 1 0 1 0 0 0 252 1 1 0 1 0 0 0 0 253 1 0 1 0 0 0 0 0 254 0 1 0 0 0 0 0 0 255 1 0 0 0 0 0 0 0 clkn clkp n n + 1 n + 2 n + 3 n + 4 n + 5 n + 4 n n + 6 n + 3 n + 5 n + 8 n + 7 n + 1 n + 2 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 n + 12 n + 13 n + 14 n + 15 n + 16 n + 17 n + 18 n + 19 adc sample number adc samples on the rising edge of clkp t pwh t pwl t clk t pd2 t pd1 dcon dcop porta data portb data note: the latency to the d port is 7.5 clock cycles, the latency to the c port is 8.5 clock cycles, the latency to the b port is 9.5 clock cycles, and the latency to the a port is 10.5 clock cycles. all data ports (porta, portb, portc, and portd) are updated on the rising edge of the dcop clock. portc data portd data sample here figure 6. timing diagram for sdr mode, f clk / 4 mode
MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs 20 ______________________________________________________________________________________ clkn clkp adc sample number adc samples on the rising edge of clkp t pd1ddr t pd2ddr dcon dcop porta data portb data note: the latency to the d port is 7.5 clock cycles, the latency to the c port is 8.5 clock cycles, the latency to the b port is 9.5 clock cycles, and the latency to the a port is 10.5 clock cycles. all data ports (porta, portb, portc, and portd) are updated on the rising edge of the dcop clock. portc data portd data sample here n n + 1 n + 2 n + 3 n + 4 n + 5 n + 4 n n + 6 n + 3 n + 5 n + 8 n + 7 n + 1 n + 2 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 n + 12 n + 13 n + 14 n + 15 n + 16 n + 17 n + 18 n + 19 figure 7. timing diagram for ddr mode, f clk / 8 mode clkn clkp adc sample number adc samples on the rising edge of clkp t pd1qdr t pd2qdr dcon dcop porta data portb data note: the latency to the d port is 7.5 clock cycles, the latency to the c port is 8.5 clock cycles, the latency to the b port is 9.5 clock cycles, and the latency to the a port is 10.5 clock cycles. all data ports (porta, portb, portc, and portd) are updated on the rising edge of the dcop clock. portc data portd data sample here from dll in fpga n n + 1 n + 2 n + 3 n + 4 n + 5 n + 4 n n + 6 n + 3 n + 5 n + 8 n + 7 n + 1 n + 2 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 n + 12 n + 13 n + 14 n + 15 n + 16 n + 17 n + 18 n + 19 figure 8. timing diagram for qdr mode, f clk / 16 mode
MAX109 nal shift register is enabled and multiplexed with the input of the 1:4 demultiplexer, replacing the quantizer 8-bit output. the test pattern consists of 8 bits. table 3 depicts the composition of the first and last steps of the prn pattern. the entire look-up table can be down- loaded from the maxim website at www.maxim-ic.com. applications information single-ended analog inputs the MAX109 is designed to work at full speed for both single-ended and differential analog inputs; however, for optimum dynamic performance it is recommended that the inputs are driven differentially. inputs inp and inn feature on-chip, laser-trimmed 50 ? termination resistors. in a typical single-ended configuration, the analog input signal (figure 9) enters the t/h amplifier stage at the in-phase input (inp), while the inverted phase input (inn) is reverse-terminated to gndi with an external 50 ? resistor. single-ended operation allows for an input amplitude of 500mv p-p . table 4 shows a selection of input voltages and their corresponding output codes for single-ended operation. differential analog inputs to obtain a full-scale digital output with differential input drive (figure 10), 250mv p-p must be applied between inp and inn (inp = 125mv and inn = -125mv). mid- scale digital output codes (01111111 or 10000000) occur when there is no voltage difference between inp and inn. for a zero-scale digital output code, the in- phase inp input must see -125mv and the inverted input inn must see 125mv. a differential input drive is recommended for best performance. table 5 repre- sents a selection of differential input voltages and their corresponding output codes. offset adjust the MAX109 provides a control input (vosadj) to compensate for system offsets. the offset adjust input is a self-biased voltage-divider from the internal 2.5v precision reference. the nominal open-circuit voltage is one-half the reference voltage. with an input resistance (r vosadj ) of typically 50k ? , vosadj can be driven with an external 10k ? potentiometer (figure 11) con- nected between refout and gndi to correct for offset errors. for stabilizing purposes, decouple this output with a 0.01? capacitor to gndi. vosadj allows for a typical offset adjustment of ?0 lsb. clock operation the MAX109 clock inputs are designed for either sin- gle-ended or differential operation (figure 12) with flexi- 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs ______________________________________________________________________________________ 21 inp inn 0v +250mv -250mv t 500mv p-p fs analog input range v in = 250mv 500mv figure 9. single-ended analog input signal swing inp inn +125mv -125mv t 250mv fs analog input range 0v 250mv -250mv figure 10. differential analog input signal swing gndi potentiometer 10k ? refout vosadj figure 11. offset adjustment circuit clkp clkcom simplified diagram (input esd protection not shown). clkn 50 ? 1v 50 ? gndi v ee figure 12. clock input structure
MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs 22 ______________________________________________________________________________________ ble input drive requirements. each clock input is termi- nated with an on-chip, laser-trimmed 50 ? resistor to clkcom (clock-termination return). the clkcom ter- mination voltage can be connected anywhere between ground and -2v for compatibility with standard-ecl drive levels. the clock inputs are internally buffered with a pre- amplifier to ensure proper operation of the data convert- er, even with small-amplitude sine-wave sources. the MAX109 was designed for single-ended, low-phase noise sine-wave clock signals with as little as 100mv amplitude (-10dbm), thereby eliminating the need for an external ecl clock buffer and its added jitter. single-ended clock inputs (sine-wave drive) excellent performance is obtained by ac- or dc-cou- pling a low-phase-noise sine-wave source into a single clock input (figure 13a, table 6). for proper dc bal- ance, the undriven clock input should be externally table 4. digital output codes corresponding to a dc-coupled single-ended analog input in-phase/true input (inp) inverted/complementary input (inn) out-of-range bit (dorp/dorn) output code 250mv 0 1 11111111 (full scale) 250mv - 1 lsb 0 0 11111111 0 0 0 10000000 toggles 01111111 -250mv + 1 lsb 0 0 00000001 -250mv 0 0 00000000 (zero scale) <-250mv 0 1 00000000 (out of range) table 5. digital output codes corresponding to a dc-coupled differential analog input in-phase/true input (inp) inverted/complementary input (inn) out-of-range bit (dorp/dorn) output code 125mv -125mv 1 11111111 (full scale) 125mv - 0.5 lsb -125mv + 0.5 lsb 0 11111111 0 0 0 10000000 toggles 01111111 -125mv + 0.5 lsb 125mv - 0.5 lsb 0 00000001 -125mv 125mv 0 00000000 (zero scale) <-125mv >+125mv 1 00000000 (out of range) table 6. driving options for dc-coupled clock clock drive clkp clkn clkcom reference single-ended sine wave -10dbm to +15dbm externally terminated to gndi with 50 ? gndi figure 13a differential sine wave -10dbm to +10dbm -10dbm to +10dbm gndi figure 13b single-ended ecl ecl drive -1.3v -2v figure 13c differential ecl ecl drive ecl drive -2v figure 13d table 7. demultiplexer and reset operations signal/pin name type functional description clkp/clkn sampling clock inputs master adc timing signal. the adc samples on the rising edge of clkp. dcop/dcon lvds outputs data clock output (lvds). output data changes on the rising edge of dcop. rstinp/rstinn lvds inputs d em ul ti p l exer r eset i np ut si g nal s. resets the i nter nal d em ul ti p l exer w hen asser ted . rstoutp/rstoutn lvds outputs reset outputs for synchronizing the resets of multiple external devices.
MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs ______________________________________________________________________________________ 23 50 ? reverse-terminated to gndi. the dynamic perfor- mance of the data converter is essentially unaffected by clock-drive power levels from -10dbm to +10dbm. the MAX109 dynamic performance specifications are determined by a single-ended clock drive of 10dbm. to avoid saturation of the input amplifier stage, limit the clock power level to a maximum of 15dbm. differential clock inputs (sine-wave drive) the advantages of differential clock drive (figure 13b, table 6) can be obtained by using an appropriate balun transformer to convert single-ended sine-wave sources into differential drives. the precision on-chip, laser-trimmed 50 ? clock-termination resistors ensure excellent amplitude matching. see the single-ended clock inputs (sine-wave drive) section for proper input amplitude requirements. single-ended clock inputs (ecl drive) configure the MAX109 for single-ended ecl clock drive by connecting the clock inputs as shown in figure 13c and table 6. a well-bypassed v bb supply (-1.3v) is essential to avoid coupling noise into the undriven clock input, which would degrade dynamic perfor- mance. differential clock inputs (ecl drive) drive the MAX109 from a standard differential ecl clock source (figure 13d, table 6) by setting the clock termination voltage at clkcom to -2v. bypass the clock termination return (clkcom) as close to the adc as possible with a 0.01? capacitor connected to gndi. demultiplexer reset operation the MAX109 features an internal 1:4 demultiplexer that reduces the data rate of the output digital data to one- quarter the sample clock rate. a reset for the demulti- plexer is necessary when interleaving multiple MAX109 converters and/or synchronizing external demultiplex- ers. the simplified block diagram of figure 1 shows that the demultiplexer reset signal path consists of four main circuit blocks. from input to output, they are the reset input dual latch, the reset pipeline, the demulti- plexer clock generator, and the reset output. the sig- nals associated with the demultiplexer-reset operation and the control of this section are listed in table 7. reset input dual latch the reset input dual-latch circuit block accepts lvds reset inputs. for applications that do not require a syn- chronizing reset, the reset inputs may be left open. figure 14 shows a simplified schematic of the reset input structure. to latch the reset input data properly, the setup time (t su ) and the data-hold time (t hd ) must be met with respect to the rising edge of the sample clock. the timing diagram of figure 15 shows the tim- ing relationship of the reset input and sampling clock. reset pipeline the next section in the reset signal path is the reset pipeline. this block adds clock cycles of latency to the clkp clkn = 0v +0.5v -0.5v note: clkcom = 0v t figure 13a. single-ended clock input?ine-wave drive clkp clkn +0.5v -0.5v t note: clkcom = 0v figure 13b. differential clock input?ine-wave drive clkp -0.8v -1.8v t clkn = -1.3v note: clkcom = -2v figure 13c. single-ended clock input?cl drive clkp clkn -0.8v -1.8v t note: clkcom = -2v figure 13d. differential clock input?cl drive
MAX109 reset signal to match the latency of the converted ana- log data through the adc. in this way, when reset data arrives at the rstoutp/rstoutn lvds output it will be time-aligned with the analog data present in data ports porta, portb, portc, and portd at the time the reset input was deasserted. demultiplexer clock generator the demultiplexer clock generator creates the clocks required for the different modes of demultiplexer opera- tion. ddr and qdr control the demultiplexed mode selection, as described in table 2. the timing diagrams in figures 6, 7, and 8 show the output timing and data alignment for sdr, ddr, and qdr modes, respective- ly. the phase relationship between the sampling clock at the clkp/clkn inputs and the dco clock at the dcop/dcon outputs is random at device power-up. reset all MAX109 devices to a known dco phase after initial power-up for applications such as interleaving, where two or more MAX109 devices are used to achieve higher effective sampling rates. this synchro- nization is necessary to set the order of output samples between the devices. resetting the converters accom- plishes this synchronization. the reset signal is used to force the internal counter in the demultiplexer clock- generator block to a known phase state. reset output finally, the reset signal is presented in true lvds for- mat to the last block of the reset signal path. rstout outputs the time-aligned reset signal, used for resetting additional external demultiplexers in applications that need further output data-rate reduction. many demulti- plexer devices require their reset signal to be asserted for several clock cycles while they are clocked. to accomplish this, the MAX109 dco clock will continue to toggle while rstout is asserted. when a single MAX109 device is used, no synchronizing reset is required because the order of the samples in the out- put ports remains unchanged, regardless of the phase of the dco clock. in all modes, rstout is delayed by 7.5 clock cycles, starting with the first rising edge of clkp following the falling edge of the rstinp signal. with the next reset cycle portd data shows the expect- ed and proper data on the output, while the remaining three ports (porta, portb, and portc) keep their previ- ous data, which may or may not be swallowed , depending on the power-up state of the demultiplexer clock generator. with the next cycle, the right data is presented for all four ports in the proper order. the aforementioned reset output and data-reset operation is valid for sdr, ddr, and qdr modes. die temperature measurement the die temperature of the MAX109 can be determined by monitoring the voltage v tempmon between the tempmon output and gndi. the corresponding volt- age is proportional to the actual die temperature of the converter and can be calculated as follows: t die (?) = [(v tempmon - v gndi ) 1303.5] - 371 the MAX109 exhibits a typical tempmon voltage of 0.35v, resulting in an overall die temperature of +90?. the converter? die temperature can be lowered con- siderably by cooling the MAX109 with a properly sized heatsink. adding airflow across the part with a small fan can further lower the die temperature, making the sys- tem more thermally manageable and stable. thermal management depending on the application environment for the sbga-packaged MAX109, the user can apply an exter- nal heatsink with integrated fan to the package after board assembly. existing open-tooled heatsinks with 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs 24 ______________________________________________________________________________________ rstinp 50% 50% clkp clkn rstinn 50% t su t hd figure 15. timing relationship between sampling clock and reset input 500 ? 500 ? 100k ? rstinp rstinn simplified diagram (input esd protection not shown) gndd v cc o v cc o figure 14. reset circuitry?nput structure
integrated fans are available from co-fan usa (e.g., the 30-1101-02 model, which is used on the evaluation kit of the MAX109). this particular heatsink with inte- grated fan is available with pre-applied adhesive for easy package mounting. bypassing/layout/power supply grounding and power-supply decoupling strongly influ- ence the MAX109? performance. at a 2.2ghz clock frequency and 8-bit resolution, unwanted digital crosstalk may couple through the input, reference, power supply, and ground connections and adversely influence the dynamic performance of the adc. therefore, closely follow the grounding and power-sup- ply decoupling guidelines (figure 17). maxim strongly recommends using a multilayer printed circuit board (pcb) with separate ground and power-supply planes. since the MAX109 has separate analog and digital ground connections (gnda, gndi, gndr, and gndd, respectively), the pcb should feature separate analog and digital ground sections connected at only one point (star ground at the power supply). digital signals should run above the digital ground plane, and analog signals should run above the analog ground plane. keep digital signals far away from the sensitive analog inputs, reference inputs, and clock inputs. high-speed signals, including clocks, analog inputs, and digital out- puts, should be routed on 50 ? microstrip lines, such as those employed on the MAX109 evaluation kit. the MAX109 has separate analog and digital power- supply inputs: ? v ee (-5v) is the analog and substrate supply ? v cc i (5v) to power the t/h amplifier, clock distribu- tion, bandgap reference, and reference amplifier ? v cc a (5v) to supply the adc? comparator array ? v cc o (3.3v) to establish power for all lvds-based circuit sections ? v cc d (5v) to supply all logic circuits of the data con- verter the MAX109 v ee supply contacts must not be left open while the part is being powered up. to avoid this condi- tion, add a high-speed schottky diode (such as a motorola 1n5817) between v ee and gndi. this diode prevents the device substrate from forward biasing, which could cause latchup. all supplies should be decoupled with large tantalum or electrolytic capacitors at the point they enter the pcb. for best performance, bypass all power supplies to the appropriate grounds with a 330? and 33? tantalum capacitor to filter power- supply noise, in parallel with 0.1? capacitors and high- quality 0.01? ceramic chip capacitors. each power MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs ______________________________________________________________________________________ 25 clkn clkp adc sample number adc samples on the rising edge of clkp t su t hd dcon reset input rstinn rstinp dcop porta data portb data portc data portd data sample here resetout data port rstoutn rstoutp the gray areas indicate a power-up dependent state, which is unknown at the time the reset is being asserted. n n + 1 n + 2 n + 3 n + 4 n + 5 n + 4 n + 6 n + 5 n + 8 n + 7 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 n + 12 n + 13 n + 14 n + 15 n + 16 n + 17 n + 18 n + 19 figure 16. reset output timing in demultiplexed sdr mode
MAX109 supply for the chip should have its own 0.01? capaci- tor, which should be placed as close as possible to the MAX109 for optimum high-frequency noise filtering. static/dc parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. for the MAX109, this straight line is between the endpoints of the transfer function, once offset and gain errors have been nullified. inl deviations are measured at every step of the transfer function and the worst-case devia- tion is reported in the electrical characteristics table. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. for the MAX109, dnl deviations are measured at every step of the transfer function and the worst-case devia- tion is reported in the electrical characteristics table. offset error offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. ideally, the mid-scale MAX109 transition occurs at 0.5 lsb above mid scale. the offset error is the amount of deviation between the measured mid-scale transition point and the ideal mid- scale transition point. bit error rates errors resulting from metastable states may occur when the analog input voltage (at the time the sample is taken) falls close to the decision point of any one of the input comparators. here, the magnitude of the error depends on the location of the comparator in the com- parator network. if it is the comparator for the msb, the error will reach full scale. the MAX109? unique encod- ing scheme solves this problem by limiting the magni- tude of these errors to 1 lsb. dynamic/ac parameter definitions signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc? reso- lution (n bits): snr[max] = 6.02 x n + 1.76 in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spec- tral components to the nyquist frequency excluding the fundamental, the first 15 harmonics (hd2 through hd16), and the dc offset: snr = 20 x log (signal rms / noise rms ) signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to the rms noise plus distortion. rms noise plus 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs 26 ______________________________________________________________________________________ 330 f gndd v cc d gnda v cc a gndi v cc i gndi 1n5817 v ee v cc a = +4.75v to +5.25v v cc d = +4.75v to +5.25v v cc i = +4.75v to +5.25v v cc o = +3.0v to v cc d v ee = -4.75v to -5.25v note: locate all 0.01 f capacitors as close as possible to the MAX109 device. gndd v cc o 33 f 0.1 f 0.01 f 0.01 f 0.01 f 0.01 f 330 f33 f 0.1 f 330 f33 f 0.1 f 0.01 f 0.01 f 0.01 f 0.01 f 330 f33 f 0.1 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 0.01 f 330 f 33 f 0.1 f figure 17. MAX109 decoupling and bypassing recommendations
distortion includes all spectral components to the nyquist frequency excluding the fundamental and the dc offset. effective number of bits (enob) enob indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob is calculated from a curve fit referenced to the theoreti- cal full-scale range. total harmonic distortion (thd) thd is the ratio of the rms sum of the first 15 harmon- ics of the input signal to the fundamental itself. this is expressed as: where v1 is the fundamental amplitude, and v 2 through v 16 are the amplitudes of the 2nd- through 16th-order harmonics (hd2 through hd16). spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next largest spurious component, excluding dc offset. third-order intermodulation (im3) im3 is the total power of the third-order intermodulation product to the nyquist frequency relative to the total input power of the two input tones, f in 1 and f in 2. the individual input tone levels are at -7dbfs. the third-order intermodulation products are located at 2 x f in1 -f in2 , 2 x f in2 -f in1 , 2 x f in1 +f in2 , and 2 x f in2 +f in1 . full-power bandwidth a large -1dbfs analog input signal is applied to an adc and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3db. this point is defined as full- power input bandwidth frequency. thd 20 log vv v 2 2 3 2 1 = +++ ? ? ? ? ? ? ? ? ... v 16 2 MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs ______________________________________________________________________________________ 27
package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) super bga.eps package outline, 25x25 / 27x27 mm sbga 21-0073 2 1 e 192 / 256 balls, 1.27 mm pitch MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs 28 ______________________________________________________________________________________
MAX109 8-bit, 2.2gsps adc with track/hold amplifier and 1:4 demultiplexed lvds outputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 29 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) package outline, 25x25 / 27x27 mm sbga 21-0073 2 2 e 192 / 256 balls, 1.27 mm pitch cardenas note: the MAX109 is packaged in a 27mm x 27mm, 256 sbga package.

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